IP108：LAN以太网芯片 IP108：
产品简介
IP108： Octal 10/100 Fast Ethernet Transceiver
产品详细信息
general desc-ription
the ip108 is a highly integrated octal phy transceiver for 10base-t, 100base-tx and 100base-fx fast ethernet applications. this device is implemented with advanced 0.18um cmos process technology for low power consumption. for the high port count switch design such as 16 or 24 or 32-port, the ip108 can simplify the system design and ensure the targeted performance.
the ip108 can be programmed to operate in various modes through either hardware (hardware strapping pin) or software control (registers setting via smi). it also supports rmii/ss-smii by setting the external hardware strapping pins during power-on reset.
the ip108 contains eight independent 10/100m phy transceiver and includes encoder, decoder, line driver, adc, dac, dsp and pll circuits for each port. the ip108 enters the automatic power saving mode to lower the power consumption once the link partner is disconnected. the ip108 just needs an external osc or crystal as the clock source, simplifying the system design. besides the features described above, the driving capability of ip108 can be trimmed to minimize the emi effect by the advanced slew rate control technology,.
feature
-integrates eight-port 10base-t, 100base-tx and 100base-fx transceivers in a single chip
-supports auto mdix function and auto-negotiation
-flexible functional configuration through either pin setting or register programming
-supports rmii/ss-smii interfaces
-support baseline wander (blw) compensation
-provides direct drive mode and serial data latch led display mode
-embeds dsp-based phy transceiver technology to improve the cable driving performance
-adjustable current driving capabilities
-provides power-on led diagnostic function
-power supply: se-lectable 3.3v/1.8v for i/o 1.8v power supply for core
-supports automatic power saving (aps) mode
-requires only one external clock source
-0.18u cmos technology
-128pin pqfp package
the ip108 is a highly integrated octal phy transceiver for 10base-t, 100base-tx and 100base-fx fast ethernet applications. this device is implemented with advanced 0.18um cmos process technology for low power consumption. for the high port count switch design such as 16 or 24 or 32-port, the ip108 can simplify the system design and ensure the targeted performance.
the ip108 can be programmed to operate in various modes through either hardware (hardware strapping pin) or software control (registers setting via smi). it also supports rmii/ss-smii by setting the external hardware strapping pins during power-on reset.
the ip108 contains eight independent 10/100m phy transceiver and includes encoder, decoder, line driver, adc, dac, dsp and pll circuits for each port. the ip108 enters the automatic power saving mode to lower the power consumption once the link partner is disconnected. the ip108 just needs an external osc or crystal as the clock source, simplifying the system design. besides the features described above, the driving capability of ip108 can be trimmed to minimize the emi effect by the advanced slew rate control technology,.
feature
-integrates eight-port 10base-t, 100base-tx and 100base-fx transceivers in a single chip
-supports auto mdix function and auto-negotiation
-flexible functional configuration through either pin setting or register programming
-supports rmii/ss-smii interfaces
-support baseline wander (blw) compensation
-provides direct drive mode and serial data latch led display mode
-embeds dsp-based phy transceiver technology to improve the cable driving performance
-adjustable current driving capabilities
-provides power-on led diagnostic function
-power supply: se-lectable 3.3v/1.8v for i/o 1.8v power supply for core
-supports automatic power saving (aps) mode
-requires only one external clock source
-0.18u cmos technology
-128pin pqfp package
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